发明名称 +-QUINARY MULTIPLICATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a ± quinary multiplication circuit faster in operation than by binary. SOLUTION: The present same products i are collected in an OR gate group by an A×B table, an AND gate is placed on the intersected point of these signals and a carry c and the gate is defined as a temporary partial product n. A special AND gate is provided on an i anti 4 and an i 4 line and the gate is made to perform a special sum anti 4 + anti 2=|4|, 4+2=|4|. The condition of a code is determined, a code AND gate group is made by this condition, and outputs are collected in an OR gate ns and are delivered to a code output N2 . A carry circuit in which the value of A×B of ± quinary numbers A and B of a figure are collected for every kind of C and the both of the same and different code signals e of a number A to be multiplied of two figures and an anti e are turned on is made. For every Q code N3 , N2 , N1 and N0 for an i signal, the final product table by i and c is made, and a final part product circuit in which the i is put in an ORr for every line on the same c and e and an AND d→N having the c and e ahead r is made is made.
申请公布号 JPH0934690(A) 申请公布日期 1997.02.07
申请号 JP19950212306 申请日期 1995.07.18
申请人 SUGIMURA YUKICHI 发明人 SUGIMURA YUKICHI
分类号 G06F7/52;G06F7/496;G06F7/523 主分类号 G06F7/52
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