发明名称 CLOCK REPRODUCTING DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce the frequency jitter of a reproduced clock generated by the fluctuation of a voltage control signal inputted to a voltage control oscillator when a clock reproduction mode is switched. SOLUTION: When a clock reproduction mode informing signal 117 is an SRTS clock reproduction mode, a selector 134 outputs an intermediate value signal 132 to an adaptive clock reproduction low pass filter 135. The adaptive clock reproduction low pass filter 135 sets an adaptive clock reproduction voltage control signal 116 to a middle signal level between a high level and a low level. Thus, the fluctuation amount of the voltage control signal 118 when the clock reproduction mode is switched from the SRTS clock reproduction mode to an adaptive clock reproduction mode is reduced.
申请公布号 JPH0936846(A) 申请公布日期 1997.02.07
申请号 JP19950177772 申请日期 1995.07.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 FUKUI AKITO;MATSUURA TAKEO
分类号 H03L7/00;H04L7/00;H04L7/033 主分类号 H03L7/00
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