BUILT IN SELF TEST (BIST) FOR MULTIPLE RAMS

摘要

Multiple embedded RAMs are tested, one at a time, for stuck at faults, including multibit faults. Parity for the RAMs is also tested and tests are performed for marginal read/write problems by changing clock frequency. A lockup mechanism yields the failing address. To accomplish the test, the RAM write address is written as data and then read back. Since the address is written as data, the expected result in a read operation is known. Thus, failures are predicted by comparing the reference address in a read cycle with the data read from the RAM. This operation is then repeated by writing the inverse write address as data. Through the two sets of write/read/compare operations, every RAM bit is toggled. After performing the two operations for one RAM, the procedure is repeated for each RAM until all have been tested. In a second embodiment, multiple embedded RAMs are tested simultaneously with the same address and data lines going to all RAMs. As with the first embodiment, testing is for stuck at faults, including multibit faults; parity for the RAMs is also tested as re-marginal read/write problems. The data patterns include the write address as data, inverse write address as data, or random data. In the second embodiment, the same data is simultaneously written into multiple RAMs, followed by a read/compare cycle. The comparison determines whether there is an error. As in the first embodiment, a look-up mechanism yields the failing address. Since, in this second embodiment, it does not matter what data is written to the RAMs, this embodiment provides the additional capability of utilizing random data to test for additional fault conditions.