| 摘要 |
A semiconductor tester which fetches a clock signal generated from a device to be tested, stabilizes the clock signal by removing jitter components, and uses the stabilized clock signal to operate the device. The tester includes a frequency divider A (11) which receives the clock signal (21) from the device to be tested, a phase detecting circuit (12), a loop filter (13), a VCO (14), a frequency divider B (16), a test period generator (15), and an interleave circuit (18). The clock signal outputted from the VCO (14) is inputted to the test period generator (15) to produce a test period signal (23), which is distributed to internal circuits of the device and, at the same time, is fed back to the phase detector (12) through the frequency divider B (16). |
