| 摘要 |
<p>PROBLEM TO BE SOLVED: To narrow the distributing width of the thresholds of memory cells even when writing is made at a high speed without verification so that readout can also be performed at a high speed. SOLUTION: In an EEPROM having a memory cell array in which N-type wells 2 and 3 are separately provided in a periphery control section and cell array section on a p-type Si substrate 1 and electrically rewritable memory cells constituted by forming floating gates 8a-8d and control gates 9a-9d on the n-type well of the cell array section are arranged in a matrix-like state, the floating gates 8 are composed of Si layers doped with p-type impurities.</p> |
