| 摘要 |
<p>A semiconductor storage device, in which a memory cell array is divided into a plurality of blocks and a word line laid within each block is boosted. Each cell (10) is formed at each intersection of a plurality of columns of paired bit lines (BL, BL) and a plurality of rows of word lines, and connected to the corresponding paired bit lines and the corresponding word line. The cell array is divided into a plurality of memory cell blocks (120). The storage device is provided with a first line to be boosted (VLINE1) which is commonly used for boosting all word lines (WL) in the memory cell blocks, boosting circuit (30) composed of a boosting capacitor (C1) connected to the first line (VLINE1) and switching transistor (T7) which precharges the capacitor (C1), and boosting control circuit (40) which outputs a precharge control signal (2) that precharges the capacitor (C1) by turning on the transistor (T7) and boosting driving signal (1) that changes the potential at the negative terminal of the capacitor (C1) to the circuit (30). In each memory cell block, a second line (VLINE2) to be boosted is provided. One memory cell block is selected by means of a block selecting circuit (90) and one word line selected by means of line selecting circuits (60 and 100) is boosted through the first and second lines (VLINE1 and VLINE2).</p> |
