| 摘要 |
<p>A phase-locked loop (PLL) frequency synthesizer is described that both reduces frequency channel spacing and accelerates convergence, and moreover, suppresses the occurrence of spurious noise. A frequency dividing circuit of the PLL frequency synthesizer is composed of a plurality of frequency dividers (7). By means of a timing generation circuit (6) that is operated by frequency signals from an external oscillation circuit, each of frequency dividers are sequentially delayed by each cycle, and the output of these frequency dividers is taken as feedback signals of the phase comparator (2) of the phase-locked loop. <IMAGE></p> |
