发明名称
摘要 In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. A line decoder is responsive to the input address for selecting one of the lines of the normal memory cells, and is inactivated by the output of the comparator when the input address is found to coincide with the programmed address. An input address to the line decoder is applied before the same input address is applied to the comparator.
申请公布号 JP2577724(B2) 申请公布日期 1997.02.05
申请号 JP19860180600 申请日期 1986.07.31
申请人 MITSUBISHI ELECTRIC CORP 发明人 FURUYA KYOHIRO;MASUKO KOICHIRO;MATSUDA YOSHIO;ARIMOTO KAZUTAMI;MATSUMOTO NORIMASA
分类号 G11C11/401;G11C11/408;G11C29/00;G11C29/04;(IPC1-7):G11C29/00 主分类号 G11C11/401
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