发明名称 Mos termination for low power signaling
摘要 A low power termination method and apparatus. The termination circuit is typically coupled to a bus through an interface node to receive a rising edge of an input voltage signal. A clamping device is coupled to the interface node and coupled to receive a clamping voltage, the clamping voltage being less than a termination voltage. The termination circuit also includes a bias supply providing a bias voltage. A control terminal of the clamping device is coupled receive the bias voltage, and clamps the interface node when the input voltage signal exceeds a termination voltage. A bias excursion of the bias voltage may be provided responsive to the rising edge so that the clamping device clamps the interface node before the input voltage signal exceeds the termination voltage. Similarly, a second clamping device biased by a second bias supply may be used. The second clamping device clamps the interface node after the input voltage signal falls below an expected low voltage. The second bias supply can provide an excursion responsive to a falling edge of the input voltage signal so that the second clamping device clamps the interface node before the input voltage falls below the expected low voltage.
申请公布号 AU5679996(A) 申请公布日期 1997.02.05
申请号 AU19960056799 申请日期 1996.05.14
申请人 INTEL CORPORATION 发明人 MICHAEL J. ALLEN
分类号 H03K19/0185;H04L25/02 主分类号 H03K19/0185
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