发明名称 Built-in self tests for large multiplier, adder, or subtractor
摘要 A method of testing a two-input multiplier, adder, or subtractor implementation for stuck-at faults includes a multi-step procedure for iteratively exercising all input and output permutations, and pseudo-exhaustively exercising all internal nodes. The method of testing a multiplier, adder, or subtractor involves logically partitioning the multiplication, addition, or subtraction into several smaller but identical independent operations. This logical partitioning of operations ensures that the output result will consist of several smaller identical results if the unit under test is functioning properly. Because the several smaller results are identical, comparing the smaller results to each other detects any failures internal to the multiplier, adder, or subtractor under test. The logically partitioned operations are repeated for multiple input setting to ensure a high level of fault coverage. In the testing of a multiplier, a four step iterative method fully exercises the multiplier. Each step includes iteratively filling alternate digits of one input operand with a first test value and filling the remaining digits of that operand with zero. Each step further includes the filling of one digit of the other multiplier operand with a second test value, while all remaining digits of that operand are filled with zero. Four different fill patterns are used for all permutations of the two test digits to fully exercise the multiplier. In the testing of an adder or subtractor, a two step iterative method fully exercises the adder or subtractor.
申请公布号 US5600658(A) 申请公布日期 1997.02.04
申请号 US19950545509 申请日期 1995.10.19
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 QURESHI, FAZAL U. R.
分类号 G01R31/3183;(IPC1-7):G06F11/22;G06F11/263 主分类号 G01R31/3183
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