发明名称 Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance
摘要 In a process for manufacturing a bipolar transistor, an intrinsic base is formed by a selective epitaxial growth while the lower surface of a base electrode single crystal silicon film 33 and the surface of a collector epitaxial layer 3 are exposed. In this process, the intrinsic base 8 and an extrinsic base 34 are grown as a single crystal to form a self-alignment type bipolar transistor having a reduced parasitic capacitance between the base and the collector.
申请公布号 US5599723(A) 申请公布日期 1997.02.04
申请号 US19960626441 申请日期 1996.04.02
申请人 NEC CORPORATION 发明人 SATO, FUMIHIKO
分类号 H01L29/73;H01L21/20;H01L21/331;H01L29/732;(IPC1-7):H01L21/70 主分类号 H01L29/73
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