Analysis system for the delay time in logic equipment

摘要

The logic equipment delay time analysis system provides not only a number of parallel dedicated delay time processors which perform calculation of the delay time, but also a processor-to-processor communications device which is connected to each of the delay time processors and performs communications between these delay time processors. The circuit model of the logic equipment is divided by a circuit model division section into a number of small logic circuits, Data with regard to each of the divided circuit models is assigned to the individual delay time processors and initial values are set into each of the delay time processors, so that the delay times for all paths from each pin at which a signal is input to circuits at which output signals are generated are calculated.