Counterflow pipeline processor with instructions flowing in a first direction and instruction results flowing in the reverse direction

摘要

A general purpose computer capable of executing instructions of the type commonly found in multiple-address register-oriented instruction sets such as the SPARC instruction set is built from a counterflow pipeline. Communication in the pipeline flows both ways between adjacent stages and different stages in the pipeline are able to perform different instructions. Instructions flow through the pipeline in one direction, ("up") and the answers computed by previous instructions, called "results," flow in the other direction, ("down"). Comparison circuits in each stage of the pipeline permit instructions to select and copy the data values they need from the downward flowing stream of previously computed results. The comparison circuits also remove from the downward flowing stream previously computed results that would be rendered obsolete by execution of the present instruction.