发明名称 ROM TESTING CIRCUIT AND ROM CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To shorten a test time by providing a first and a second operation sections. SOLUTION: A row address out of an address AD is inputted to a row decoder 2, and a ROM cell 9 in the row direction is selected. Consequently, selected cell data of the cell 9 is transmitted to each bit line 1b respectively. A row computing element 6 performs exclusive OR of an output of the preceding stage and data in each line 1b by ExOK6a, and performs parity calculation in the row direction. On the other hand, simultaneously, a cell 11a in a row parity bit storing section 11 in the cell 11a in the selected row also is selected, a parity bit in the cell 11a is transmitted to a line 14. And the parity bit in the line 14 is compared with output data of ExOR6a of the final stage of the row computing element 6, it is discriminated whether the row direction is good or not, depending on the result. Simultaneously, test operation in the row direction is performed, the result is held in DFF7c, the data is taken to the outside of a ROM section 1 with the prescribed timing.</p>
申请公布号 JPH0927200(A) 申请公布日期 1997.01.28
申请号 JP19950172175 申请日期 1995.07.07
申请人 TOSHIBA MICROELECTRON CORP;TOSHIBA CORP 发明人 FURUYA TAKASHI
分类号 H01L27/10;G11C17/00;G11C29/00;G11C29/56;(IPC1-7):G11C29/00 主分类号 H01L27/10
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