| 摘要 |
A flexible architecture for the Super Core for implementing the FC-1 transmission protocol and the FC-2 signalling (framing) protocol in a 1.0625 Gbit/second Fibre Channel, which realizes 80 Mbytes/second sustained throughput. The architecture supports multiple, concurrent, open, and active exchanges and sequences with the use of an embedded control processor with all necessary time-critical functions performed in hardware and less critical performed by the embedded processor firmware.
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