Multiprocessor data memory sharing system in which access to the data memory is determined by the control processor's access to the program memory

摘要

In a system including a control processor, a coprocessor, a program memory and a data memory, the control processor accessing the program memory during an instruction fetch cycle and the data memory during an instruction execution cycle, an apparatus for controlling access to the data memory has a control processor interface for coupling to the control processor, a coprocessor interface for coupling to the coprocessor, and instruction fetch detection logic, coupled to the control processor interface, for detecting when the control processor requests access to the program memory and generating, in response, a first access control signal. The apparatus also has scheduling logic, coupled to the coprocessor interface, for detecting when the coprocessor requests access to the data memory and, in response, generating a second access control signal. A switch in the apparatus couples memory address, memory data and memory control signals to the data memory alternatively from the control processor or the coprocessor. A switch control signal for the switch is generated by arbitration logic, coupled to the instruction fetch detection logic, the scheduling logic, and the switch, for generating a switch control signal in response to the first and second access control signals. The detection of an instruction fetch by the control processor may be based on an instruction fetch signal issued by the control processor, or by the detection of an address generated by the control processor not being in a range associated with the data memory.