发明名称 |
Method of segmenting an FPGA channel architecture for maximum routability and performance |
摘要 |
The current invention considers automatic synthesis of segmented channel architecture of row-based FPGAs so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. For such a granular segmented channel architecture routing of long nets may require that several short segments be joined together by programming horizontal antifuses. Depending on the antifuse technology, the programmed antifuses can add considerably to the path delays. A simulated annealing based channel architecture synthesis algorithm has been developed which enhances routability and performance. The synthesis algorithm is based on the fact that a strong correlation between the spatial distribution of nets and segments in a channel improves both routability and performance.
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申请公布号 |
US5598343(A) |
申请公布日期 |
1997.01.28 |
申请号 |
US19930130605 |
申请日期 |
1993.10.01 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
ROY, KAUSHIK;NAG, SUDIP K. |
分类号 |
G06F17/50;(IPC1-7):H03K19/177;H03K17/693 |
主分类号 |
G06F17/50 |
代理机构 |
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