发明名称 |
Method of manufacturing a matrix of memory cells having control gates |
摘要 |
A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.
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申请公布号 |
US5597750(A) |
申请公布日期 |
1997.01.28 |
申请号 |
US19950474735 |
申请日期 |
1995.06.07 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.R.L. |
发明人 |
PIO, FEDERICO;RIVA, CARLO;LUCHERINI, SILVIA |
分类号 |
G11C16/04;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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