CLOCK RECOVERY CIRCUIT AND RECEIVER USING SAME

摘要

PROBLEM TO BE SOLVED: To realize a reduced circuit scale in which a convergence speed and response performance are improved regardless of multi-level processing number in the clock recovery circuit of a demodulator processing multi-level PSK and multi-level QAM or the receiver using the same. SOLUTION: This circuit is provided with a phase error detection circuit 90 in which high pass filtering is applied to optional data and data in the vicinity of the optional data among a data string sampled by a recovered clock whose frequency is twice a symbol rate and which obtains a clock phase error based on the arithmetic result and a difference of two data adjacent to the optional data. The output is integrated by a loop filter 13 and a voltage controlled oscillator 14 controls the recovered clock.