| 摘要 |
This invention is a process for fabricating a dynamic random access memory (DRAM) having a stacked capacitor with hemispherical-grain (HSG) polysilicon asperities on an amorphous silicon storage-node plate. The process enables the selective formation of HSG polysilicon asperities on the storage-node plates and a subsequent deposition of a high-quality silicon nitride cell dielectric layer on the asperity-covered storage-node plates. The process is preferably initiated following field oxide formation, wordline formation, access transistor source/drain region formation, deposition of a planarizing dielectric layer, formation of bitline contact and storage-node contact openings in the planarizing layer, and formation of conductive plugs in both types of contact openings. The process is implemented by sequentially depositing a first tetraethylorthosilicate (TEOS) oxide layer, a first silicon nitride layer, a second TEOS oxide layer, a second silicon nitride layer, and a boro-phospho-silicate glass (BPSG) layer to form a multi-layer partly-sacrificial stack. Depressions are etched in the partly-sacrificial stack and amorphous silicon cup-shaped storage-node plates are formed in the depressions. Following removal of the BPSG layer and the second silicon nitride layer, HSG polysilicon asperities are formed on the plates. The second TEOS oxide layer is then removed, exposing the first silicon nitride layer. A silicon nitride cell dielectric layer is then deposited over the surface of the array.
|
