| 摘要 |
<p>An apparatus and a method for testing a semiconductor memory such that the contents stored in a failure analysis memory are read out smoothly. Sequence data generated by a plurality of test pattern generators (2) are written in a memory (6) under test through the interleave operation of a first interleave circuit (71). The written data are read out through the interleave operation of a second interleave circuit (72) and dividedly fed to a plurality of logic comparators (4), which compare the test results with expected value data. When the result of comparison indicates 'fail' and the data in the interleave cycle including the fail data are dividedly stored in a plurality of failure analysis memories (5), the comparators (4) generate fail mark signals based on the fail data and the fail mark signals are correlated with fail signals and stored in the memories (5). After the test, the data cycle in which the fail occurs is identified by reading out the fail mark signals from the memories (5).</p> |
