发明名称
摘要 PURPOSE:To prevent an erroneous sub clock signal from being reproduced, by inserting a register of eight bits and a protection circuit for detecting bipolar violation into a circuit which receives and reproduces the sub clock signal of 8KHz from a composite bipolar signal. CONSTITUTION:When a composite bipolar clock signal is received with correct regularity, a coincidence decision signal can be obtained correctly at every eight bits in a coincidence decision circuit 3, and the frequency demultiplying state of a 1/8 frequency demultiplier 4 is controlled correctly, therefore, the sub clock signal of 8kHz that is 1/8 of a clock of 64kHz can be received and reproduced correctly. When a bipolar rule is received erroneously due to an unknown cause, it is not detected at a bipolar violation detection circuit 1. As a result, since no coincidence output is generated from the coincidence deci sion circuit 3, a normal frequency demultiplying operation can be continued without resetting the 1/8 frequency demultiplier 4.
申请公布号 JP2573591(B2) 申请公布日期 1997.01.22
申请号 JP19870017939 申请日期 1987.01.28
申请人 NIPPON ELECTRIC CO 发明人 DOMORI NORITOSHI
分类号 H03M5/18;H03K5/00;H04L7/04;H04L7/08 主分类号 H03M5/18
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