GATE ELECTRODE PATTERN LAYOUT OF SEMICONDUCTOR DEVICE

摘要

Disclosed is a gate electrode pattern layout for semiconductor device which prevents a notching formed at the edge of an active area when forming a gate electrode of MOSFET(Metal Oxide Semiconductor Field Effect Transistor). The gate electrode pattern layout of the semiconductor device cross an active area pattern for defining an isolation area and the active area, wherein an width of the edge of the active area is formed more largely than an width of a center of the active area. Thus, it is possible to prevent the function of the semiconductor being degraded.