Radar encoder

摘要

A radar encoder comprising a delta modulation circuit which receives analog radar video data from a radar and then converts the data to digitized NRZL video data. The radar encoder also has an encoder circuit which receives the digitized NRZL video data as well as a trigger pulse signal and analog synchro signals from the radar. The synchro signals are provided to a Synchro-to-Digital Converter which converts the synchro signals to sixteen digital synchro data bits which are then latched into the converter. The synchro data bits are next parallel transferred to a pair of shift registers and then clocked in a serial format to a multiplexer. The multiplexer also receives the digitized NRZL video data supplied to the encoder circuit. A state machine, in response to the trigger pulse signal, generates control signals to latch the synchro data bits into the converter and then effect the parallel transfer of the synchro data bits from the converter to the shift registers. The state machine also supplies control signals to the multiplexer allowing the multiplexer to first pass therethrough sixteen logic ones, followed by four logic zeros and four logic ones forming a frame sync. The multiplexer will next pass the sixteen synchro data bits therethrough followed by eight logic zeros. After the first forty eight bits of digitized data passes through the multiplexer in a serial format, the state machine provides a control signal which allows the digitized NRZL video data to pass through the multiplexer.