| 摘要 |
PROBLEM TO BE SOLVED: To reduce noise propagated from a digital circuit part to an analog circuit part and to improve an SN ratio. SOLUTION: A master clock MCK is frequency-divided into 1/n by a frequency dividing circuit 21 to obtain a timing signal TM1 for a latch circuit 11. When the signal TM1 is frequency-divided into 1/2, a signal N1 is generated. On the other hand, a timing signal TM2 for driving a switch 13 is generated by the product of the inverse signal N1 of the signal N1 and a signal N3 obtained by delaying the signal N1 by τ and a timing signal TM3 for driving a switch 14 is generated by the product of the signal N1 and a signal N4 obtained by delaying the signal N2 by τ. In this case, the value of τ is set up so as to shift the rising of the master clock MCK and the falling of the signals TM2, TM3 by prescribed time Δt. |
