发明名称 |
C-TO-N RATIO DETECTION MEANS FOR DIGITAL DEMODULATION CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To reduce the circuit scale of an LSI and to improve the calculation accuracy of the C/N by the C/N detection means of the digital demodulation circuit. SOLUTION: A square mean value calculation circuit 40 calculates a value K1 *(C+N) proportional to a sum (C+N) between a carrier power C and a noise power N. An absolute value mean calculation circuit 30 calculates a carrier amplitude Vc(=K2 *√C) and the calculated values are stored in a register file 4. Then a microprocessor 5 reads the calculated values stored in the register file 4 and the C/N is calculated from (K2 *√C)<2> /K1 *(C+N)*(K2 <2> / K1 )-(K2 *√C)<2> ). The calculation of the sum of the carrier power C and the noise power N by the square mean value calculation circuit 40 and the calculation of the carrier amplitude by the absolute value mean calculation circuit 30 are processed in an LSI and the C/N is calculated by the microprocessor 5.
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申请公布号 |
JPH0923250(A) |
申请公布日期 |
1997.01.21 |
申请号 |
JP19950173124 |
申请日期 |
1995.07.10 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
SAKA HIROSHI;URATA KAZUNAO;SOGA SHIGERU |
分类号 |
H04L27/00;H04L27/18;(IPC1-7):H04L27/18 |
主分类号 |
H04L27/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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