发明名称 METHOD OF FORMING MULTILAYERED WIRING STRUCTURE OF SEMICONDUCTOR DEVICE
摘要 A conductive film is formed on first and second prospective lower wiring layer formation regions on a semiconductor substrate and a prospective isolation region between the lower wiring layers. An insulating interlayer is formed on the semiconductor substrate including this conductive film and is partially removed to obtain an opening in which the conductive film is exposed. In addition, an upper wiring layer is formed on the upper surface of the semiconductor substrate. The conductive film and an upper wiring portion located on the conductive film are simultaneously and selectively removed to obtain isolated upper layer portions and isolated conductive film portions. Alternatively, two wiring portions each having at least two lower wiring portions electrically insulated from each other and adjacent to each other are formed on a semiconductor substrate having a stepped portion, and an insulating interlayer is formed thereon. The insulating interlayer is removed until the first and second wiring portions are exposed. In addition, the stepped portion formed in the second wiring portion is buried with a third insulating film. A method of forming a highly reliable multilayered wiring structure at a high yield can be obtained.
申请公布号 KR970000970(B1) 申请公布日期 1997.01.21
申请号 KR19930003960 申请日期 1993.03.16
申请人 TOSHIBA KK. 发明人 SUNADA, TAKESHI;MASE, YASUKAZU
分类号 H01L21/768;H01L23/522;(IPC1-7):H01L21/768 主分类号 H01L21/768
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