发明名称 BUFFER MEMORY DEVICE AND METHOD FOR CONTROLLING ADDRESS
摘要 <p>PURPOSE: To provide a buffer memory device contriving to reduce the access operation speed for a buffer memory temporarily storing the data inputted via plural input lines. CONSTITUTION: When N storage devices 1100-i corresponding to N input lines are assigned and input data #1 to #N to be processing object is inputted via each input line, the input data is temporarily sotred in the corresponded storage devices 1100-i. At the time, the writing address is acquired from the head of the queue of the empty address controlled by a writing address generator 1200-i, and the writing address is added to the queue of a reading address with the identification data of the storage device in which the data is written by a reading address generator 1300. When data is read, the address of the data of the reading object is acquired from the head of the queue of the reading address and is added to the end of the queue of the idle address by the corresponding writing address generator 1200-i.</p>
申请公布号 JPH0918482(A) 申请公布日期 1997.01.17
申请号 JP19950166619 申请日期 1995.06.30
申请人 TOSHIBA CORP 发明人 MOTOYAMA MASAHIKO;NOGAMI KAZUO
分类号 H04Q3/00;H04L12/28;H04L12/865;H04L12/879;H04L12/931;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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