| 摘要 |
PROBLEM TO BE SOLVED: To eliminate the need of a synchronizing processing among respective processors and to perform a high-speed test by allocating access areas inside cache memories at positions mutually different and specific to the respective processors, writing and reading data only for the specific access areas and testing a cache memory control mechanism. SOLUTION: This method tests the cache memory control mechanism for controlling data coherency between the cache memories 2A and 2B or between the cache memories 2A and 2B and a main memory unit 6. A control unit which is a mechanical minimum unit in the control of the coherency is divided corresponding to the number of processors 1A and 1B and the access areas inside the cache memories 2A and 2B at the positions mutually different and specific to the respective processors are allocated inside the divided control units. The respective processors write and read the data only for the specific access area in the same control unit and the cache memory control mechanism is tested based on the data. |
