| 摘要 |
PURPOSE: To reduce the alignment failure in the direction of both axes without changing alignment accuracy and design margin by performing alignment in the X-axis direction by the alignment mark in the X direction of a gate layer and performing alignment in the Y-axis direction by the alignment mark in the Y direction of a field layer. CONSTITUTION: When exposing a bit-wire contact layer in a MOS transistor pattern used by the memory cell of stack-capacity DRAM, alignment is made to a gate layer with the gate layer as an xth layer of an alignment layer for the X direction and is made to a field layer with a field layer as the yth layer of the alignment layer for the Y direction. That is, the alignment is made using an alignment mark 4GX in the X direction for being formed at the gate layer for the X direction and is made to an alignment mark 4GY in the Y direction formed at the field layer for the Y direction. |
