| 摘要 |
During the transmission of digital signals at gigabit rates the critical distances are so small that in usual clock retrieval circuits phase oscillations between clock and data phases are to be expected of the order of the very short bit length. A clock and data regenerator is therefore disclosed with only three D-flip-flops (DF1, DF2, DF3) and one delay unit (T/2) interconnected in parallel at the input side that receive the high bit rates of the input signal, whereas all other components are designed as a 2:1 demultiplexer and work at lower clock and data rates. To widen the capture range, developments of the invention include a frequency regulating loop connected to a downstream window discriminator or frequency detector.
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