| 摘要 |
The memory circuit holding an electrical state comprises an electrically erasable programmable read only memory (EEPROM). It includes two inverters (I1,I2), the output of one inverter (I1) being connected to the input of the second inverter (I2) and vice versa. A connection gate (P1) consists of a first N-type transistor (104) connected to the input (102) of the memory circuit (201) at the input (112) of the first inverter (I1). The output (103) of the circuit (201) is connected to the output of the second inverter (I2). The second inverter (I2) comprises a second P-type transistor (106) in series with a third N-type transistor (107). The second inverter (I2) also includes a fourth transistor (202 in series with the second and third transistors.
|
