AN INTEGRATED CIRCUIT HAVING ENABLE CONTROL CIRCUITRY

摘要

A circuit which responds to an external standby command (CE) (a transition in a chip enable signal from an external device) by generating a delayed internal standby signal (CE ADD). The internal standby signal (CE ADD) functions by switching selected components of the circuit (such as address buffers Ao through Ap) from an active mode to a standby mode. In preferred embodiments, the circuit is a memory circuit implemented as an integrated circuit. The amount of the delay in generating the delayed internal standby signal is selected to achieve a desired decreased average response time to a sequence of commands (such as memory access commands) without excessive power consumption. In embodiments in which the circuit is a memory chip (such as a flash memory chip) having address access time in the range from 60 ns to 80 ns, the delay typically is from about 100 ns to about 200 ns.