Main memory controller responsive to signals indicative of owned and unowned status

摘要

In a system bus connected to at least one CPU having a cache memory used for increasing memory access speed in an engineering workstation or the like, a main memory controller including a status memory for storing owned and unowned statuses in a main memory and a cache memory of data associated with an access operation to a system bus connected to at least one CPU having a cache memory performed by an access means of a CPU or the like, a memory control portion which is responsive to signals indicative of the stored statuses for reading the data in the main memory before the time for outputting a data invalidating signal from the cache memory elapses in the case of the owned status and for reading the data in the cache memory after the data invalidating signal is output in the case of the unowned status, and a status rewrite control portion for monitoring accesses to the system bus and for rewriting the status in the status memory according to the result of the monitoring.