| 摘要 |
An exception handler has a priority table which stores information pertaining to priorities for handling one or more concurrently generated interrupts. This table holds all possible priorities of interrupts given the numerous permutations that can arise for any set of active and non-active interrupts. The exception handler also includes a cause register that has flag bits to indicate when an interrupt has been generated. The bits in the cause register define an indexing address to a location in the priority table that contains the priority information for a given combination of active and non-active interrupts. In one implementation, the priority table stores the addresses of interrupt service routines (ISRs) for handling the highest priority active interrupt from among all currently active interrupts. In another implementation, the priority table holds index addresses to a second, ISR address table which associates the interrupts with the addresses of the corresponding ISRs that service them. The priority table effectively selects the highest priority interrupt by addressing the appropriate location in the ISR address table to extract the address of the suitable ISR. The tradeoff of these two implementations is between performance and memory size, with the single table implementation having higher performance but requiring more memory space and the double table implementation consuming less memory space but having lower performance. The exception handler of this invention is capable of dynamically adapting to various hardware requirements in terms of interrupts and priorities, as well as handling the interrupts in a real-time manner through the efficiencies gained with the priority table.
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