Open-drain fet output circuit

摘要

An input signal is inverted by an inverter in the first stage and an n-channel MOS transistor on the pull up side in a driver is driven, while an output signal of the inverter in the first stage is inverted by an inverter in the next stage and an n-channel MOS transistor on the pull down side is driven. A driving signal is output from a connection point between the n-channel MOS transistor on the pull up side and the n-channel MOS transistor on the pull down side, and an output transistor is driven by the driving signal. Since a gate voltage of the output transistor increases only by a value of a power supply voltage Vdd minus threshold voltage VT, a rise time and a fall time of a gate potential can be reduced, resulting in improvement in the duty cycle.