| 摘要 |
Pulse signals indicating up or down of a time constant are received and counted. When a time-out occurs, a time constant change signal is output. At up counting, when input signal is low, the flip-flop 80 of each bit is forcibly set to 1. Then, an up counter consisting of the high-order two bits (control bits) is provided. A time constant of a variable integrator is changed in response to output of the high-order two bits, so that the time constant can be changed rapidly. On the other hand, if the input signal is high, a 5-bit down counter is provided. Thus, the time constant of the variable integrator can be changed gently.
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