| 摘要 |
<p>PURPOSE: To improve a transmission speed subsequent to a difference in transmission time at both ends of a transfer gate inserted between circuits to which different supply voltage are fed, at the time of a level conversion between circuits. CONSTITUTION: A transfer gate N4 is provided in the device to transmit an output of a NAND circuit 1 to an inverter circuit 2. Moreover, a level conversion means for a PMOS transistor P4 is provided to pull up an input terminal of the inverter circuit 1 to the VPP potential in response to an output data from the NAND circuit 1 when the input terminal of the inverter circuit 2 connected to an output terminal of the transfer gate is pulled up to a power source potential VPP to carry out the level conversion. As compared with a conventional level conversion means which uses, as a control signal, a signal of the output terminal of the transfer gate having a large conduction resistance and a large signal delay, this conversion means avoids a signal delay without enlarging the transistor in size and reducing the conduction resistance, and an area of the circuit is not required to be increased.</p> |
