SEMICONDUCTOR MEMORY DEVICE, DATA-WRITING METHOD OF THE DEVICE AND ITS PARALLEL TESTING APPARATUS

摘要

PURPOSE: To conduct an accelerated test at high speeds flexibly without being influenced by a function or an accuracy of a testing apparatus set outside. CONSTITUTION: A test mode control circuit 19 detects from a combination of a control signal from outside and an address signal that a test mode is designated, thereby activating an internal cycle-setting circuit 20. The internal cycle- setting circuit 20 generates a clock signal of a predetermined cycle at an activation time and feeds the signal to a control circuit 18. The control circuit 18 sequentially generates an internal address signal from an internal address generation circuit 10 synchronously with the clock signal in accordance with a test mode designation signal from a test mode-setting circuit 80 and the clock signal from the internal cycle-setting circuit. As a result, a word line of a memory array 7 is selected.