发明名称 SIMULATION METHOD FOR INTEGRATED CIRCUIT
摘要 PURPOSE: To improve the quality and yield of the design of the integrated circuit by giving the channel length dependency of the current of at least an MOS transistor to parameters for a probability interpolation model. CONSTITUTION: Sample data Ids , Vds , Vga , Vbs , and L of the MOS transistor are inputted to a data processing system through an input device. Here, Ids is the drain-source current, Vds the drain-source voltage, Vgs the gate-source voltage, Vbs the base-source voltage, and L the channel length. Then parameters are adjusted for the respective channel lengths L of respective samples to constitute an interpolation model. Then the channel length dependency of a model parameterρ<2> is extracted. In this case, the probability interpolation model is used for the approximation of circuit characteristics and the parameterρ<2> which greatly affects the model shape of the probability interpolation model is given the channel length dependency of the current flowing to the MOS transistor to constitute a numeric model.
申请公布号 JPH096813(A) 申请公布日期 1997.01.10
申请号 JP19950151835 申请日期 1995.06.19
申请人 SONY CORP 发明人 RO KINKIN;OTANI JUNICHI
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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