| 摘要 |
PURPOSE: To test a device at the time of a latency operation under a predetermined condition, by delaying a cycle shift of an expectation signal from a pattern generator and a STRB signal from a timing generator. CONSTITUTION: A driver pattern generated from each pattern generator 20 is impressed as a driver waveform to a memory 10 to be tested. During a latency operation, an output data is generated with a cycle delay D. An expectation pattern is shifted at a cycle shift part 21 by a quotient D after an operation of D÷N, output as an expectation shift signal from the pattern generator 20 and shifted by a phase shifter 232 synchronously with a RATE signal output from a cycle generator 231, eventually to be output as an expectation pattern signal. An STRB signal from each timing generator to be impressed to a logic comparator 213 is generated every eXTM delay when (e) is a remainder of the operation D÷N and TM is a cycle of the memory 10 to be tested, whereby the signal is judged to be good or not to each expectation pattern. |
