| 摘要 |
PURPOSE: To process and integrate data just after switching the device into a reception mode in a simplex system. CONSTITUTION: This device is provided with JK-F/Fs 3 and 4 for outputting signals active by the extent of the lead phase difference or lag phase difference of pulse signals from edge detectors 1 and 2 for detecting the change points of received and reproduced clock signals, OR gate 6 for outputting the OR between a third pulse signal to be outputted at the falling of the received clock signal and the HOLD signal of a CPU and up/down counter 7 for executing up/down to a counted value by the signals of the JK-F/Fs 3 and 4 and loading an initial value when the output of the OR gate 6 is active and then, this device is further provided with a latch circuit 8 for holding the counted value of the counter 7 by the third pulse signal, voltage controlled oscillator(VCO) 10 for changing an oscillation frequency by a counted value converting analog signal, and frequency divider 11 for dividing the frequency of an output signal from the VCO 10 and outputting the reproduced clock signal. |
