| 摘要 |
PURPOSE: To provide stable DRAM access by preventing sensitivity from being lowered by delay time fluctuation caused by dispersion in environmental conditions such as power supply voltage or temperature or the like and processes. CONSTITUTION: This circuit is provided with a PLL circuit 1 for synchronizing the phases of external and internal clocks CK and CKi and outputting a control signal VL for this phase synchronization. Delay circuits 21-23 are respectively provided with (n), (p) and (q) pieces of serially connected delay unit elements 131 for varying delay time in response to the supply of the control signal VL. |
