| 摘要 |
PURPOSE: To provide the check point acquisition system which considerably reduces the load on a processor of cache flash executed at the time of check point acquisition. CONSTITUTION: Cache flash hardware 4a and 4b which execute the cache flash in parallel with and independently of operations of processors 2a and 2b, cache flash start parts 5a and 5b which start these cache flash hardware 4a and 4b, and cache flash completion detection parts 6a and 6b which detect the completion of cache flash are provided. At the time of check point acquisition, processors 2a and 2b execute the first cache flash in parallel with the normal processing and interrupt the normal processing at the time, when cache flash completion detection parts 6a and 6b detect the completion of the first cache flash, to not only preserve the context but also start the second cache flash. |
