| 摘要 |
PURPOSE: To provide a clock reproducing device with which a reproduced clock with a little jitter can be outputted. CONSTITUTION: This device is provided with edge detectors 1 and 2 for detecting the respective change points of received and reproduced clock signals, JK-F/Fs 3 and 4 for outputting active signals by the lead phase difference or lag phase difference of pulse signals from the edge detectors 1 and 2, and counters 5 and 6 for counting up counted values by these output signals and outputting carry-up signals when the counted values are maximum, and the counted values are counted up and down by the output signals of the counters 5 and 6. Then, this device is further provided with an up-down counter 7 for outputting its count value and the OR between both the carry-up signals, initial value varying circuit 8 for outputting the counted value just for a prescribed time although a fixed value is outputted usually and a frequency divider 9 for dividing the frequency of a system clock signal until the same frequency as the received clock signal is attained and outputting the reproduced clock signal with the counted value of the initial value varying circuit 8 changed by the time width of 'L' of the reproduced clock pulse. |
