| 摘要 |
PURPOSE: To hold the characteristics of a PLL similarly to the inactive time of a microcomputer by delaying one of clocks of the microcomputer and the PLL for prescribed time and suppressing the influence of noise caused by an operation change point and a phase difference detecting point. CONSTITUTION: A clock generating circuit 1 supplies the same clock (CK) to a phase delay circuit 2 and a reference frequency generating circuit 4 and the circuit 2 delays a 50nsCK for prescribed time, for example. A timing generator 3 to input this delayed clock CP generates a clock CM for a microcomputer 10 and supplies it to the microcomputer 10. Thus, the level change point of a reference frequency FS, namely, the phase detecting point of a phase difference signal PC and the operating point of the computer 10 are not always overlapped. Therefore, the cycle of CK at 9MHz becomes 111ns, the computer 10 is operated while being delayed for 50ns at all times, and the generation of noise caused by this delay is delayed as well. Thus, the error of the PLL caused by noise interference can be suppressed. |
