Clock multiplying apparatus using delay line loop circuitry,申请号GB19960022934-传众专利搜索

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发明名称	Clock multiplying apparatus using delay line loop circuitry
摘要
申请公布号	GB9622934(D0)	申请公布日期	1997.01.08
申请号	GB19960022934	申请日期	1996.11.04
申请人	ALTERA CORPORATION	发明人
分类号	H03K5/00;H03K5/159;H03L7/081;H03L7/16	主分类号	H03K5/00
代理机构		代理人
主权项
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