| 摘要 |
A PLL circuit 31 of a pulse convert/output circuit 12 in an NC board A 1 receives a fundamental clock signal CLK through a PC extension bus 207 from a fundamental clock generating circuit 201, and generates a sync pulse signal PLS on the basis of the received fundamental clock signal CLK. The sync pulse signal PLS is inputted to a gate 34. A signal select circuit 33 receives an address signal AD, or a RESET signal or an IRQ signal through the PC extension bus 207, and generates a pulse-outputting permission signal N3 on the basis of the received signal. The pulse-outputting permission signal N3 controls a gate 34 which determines the timing of starting the outputting of the sync pulse signal PLS. Consequently, a sync signal PLSOUT that is synchronized with those in the remaining NC boards is generated. |
