发明名称 Method of manufacturing a silicon on sapphire integrated circuit arrangement
摘要 In order to reduce the leakage current which can occur in N-channel MOS devices formed on a sapphire substrate when subject to incident radiation, a P-type layer is formed at the interface between the substrate and the epitaxial silicon in which the MOS devices are formed. The P-type layer is produced by implanting high energy silicon ions through the epitaxial silicon to back-scatter aluminium from the sapphire interface. Subsequent annealing produces a high quality crystalline structure in the silicon. The improvement in radiation hardness is substantial. <IMAGE>
申请公布号 EP0752719(A1) 申请公布日期 1997.01.08
申请号 EP19960304139 申请日期 1996.06.05
申请人 PLESSEY SEMICONDUCTORS LIMITED 发明人 KERR, JOHN ANTHONY;GARRAWAY, ANTHONY SAKARI
分类号 H01L21/265;H01L21/20;H01L21/336;H01L21/86;H01L27/12;H01L29/786 主分类号 H01L21/265
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