| 摘要 |
A technique is provided for switching circuitry in a manner which allows the circuit to respond quickly to changes in some critical input signals expected to arrive last. In the preferred embodiment the circuits of this invention are provided in triple logic column form. A circuit will typically include at least two logic columns, each having three portions serially coupled between a high and a low potential source. The middle portion of each logic column is connected to the output node and to receive the critical input signal expected to arrive last, or the input signal with the critical timing requirement. The upper and lower portions of each logic column are connected to receive the remaining input signals, that is those input signals not expected to be changing at the time the critical input signal is received. Thus, the state of the upper and lower portions of the logic column can be "set-up" in advance, in readiness for the critical input condition. Typically, the invention provides three logic columns - - - one logic column for causing the output to follow changes in the state of the critical input signals, one logic column for causing the output to have a state which is the reverse of the state of the critical input signals, and a final logic column for holding the condition of the output constant regardless of changes in the state of the critical input signals.
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